1. Field of the Invention
The present invention generally relates to manufacturing methods of wiring boards. More specifically, the present invention relates to a manufacturing method of a wiring board having a wiring formed on an insulating layer.
2. Description of the Related Art
FIG. 1 is a cross-sectional view of a related art wiring board.
As shown in FIG. 1, a related art wiring board 200 is a built-up board having a core. The wiring board 200 includes a core substrate 201, piercing electrodes 202, pads 203, insulating layers 204 and 212, wiring patterns 206, wirings 207 and 211, solder resist layers 208 and 216, via forming parts 213, and outside connection pads 214.
The core substrate 201 is a plate-shaped substrate and has piercing holes 221. The piercing electrodes 202 are provided in the piercing holes 221. The pads 203 are provided on an upper surface 201A of the core substrate 201 and upper ends of the piercing electrodes 202. Because of this, the pads 203 are electrically connected to the piercing electrodes 202.
The insulating layer 204A is provided on the upper surface 201A of the core substrate 201 so as to cover a part of the pads 203. The insulating layer 204 includes opening parts 223 exposing upper surfaces of the pads 203.
The wiring pattern 206 include the via forming parts 225 provided in the opening parts 223 and the wirings 226 formed in a body with the via forming parts 225. Each of the via forming parts 225 includes a copper (Cu) layer 228 and a Cu plating film 229. The Cu layer 228 is provided in the opening part 223. The Cu plating film 229 fills the opening part 223 where the Cu layer 228 is formed. A lower end of the via forming part 225 is connected to the pad 203.
Each of the wirings 226 is provided on the upper end of the via-forming part 225 and the upper surface 204A. The wiring 226 includes the Cu layer 228 and the Cu plating film 229. The Cu layer 228 is provided on the upper surface 204A of the insulating layer 204. The Cu plating film 229 is provided on the Cu layer 228 and the via-forming part 225. The wirings 226 have electronic component mounting pads 231 where an electronic component is mounted. The wirings 226 are electrically connected to the pads 203 via the via-forming part 225.
Each of the wirings 207 is provided on the upper surface 204A of the insulating layer 204. The wiring 207 includes the Cu layer 228 and the Cu plating film 229. The Cu layer 228 is provided on the upper surface 204A of the insulating layer 204. The Cu plating film 229 is provided on the Cu layer 228. The wiring 207 has a narrow width equal to or less than 10 μm.
The solder resist layer 208 is provided on the upper surface 204A of the insulating layer 204 so as to cover the wirings 207 and the wirings 226 except the electronic component mounting pads 231. The solder resist layer 208 has an opening 208A exposing the upper surface of each of the electronic component mounting pads 231.
Each of the wirings 211 is provided on the lower end of the piercing electrode 202 and the lower surface 201B of the core substrate 201. With this structure, the wiring 211 is electrically connected to the pad 203 via the piercing electrode 202.
The insulating layer 212 is provided on the lower surface 201B of the core substrate 201 so as to cover a part of the wirings 211. The insulating layer 212 has an opening 233 exposing a part of the lower surface of each of the wirings 211.
The via forming parts 213 are provided in the openings 233. Each of the via forming parts 213 includes a Cu layer 235 and a Cu plating film 236. The Cu layer 235 is provided in the opening part 233. The Cu plating film 236 fills the opening part 233 where the Cu layer 235 is formed. An upper end of the via forming part 213 is connected to the wiring 211.
The outside connection pads 214 are provided on the lower surface 212A of the insulating layer 212 and the lower ends of the via forming parts 213. Each of the outside connection pads 214 is formed in a body with the via forming part 213. The outside connection pad 214 includes a Cu layer 235 and a Cu plating film 236. The Cu layer 235 is provided on the lower surface 212A of the insulating layer 212. The Cu plating film 236 is provided on the lower surface of the Cu layer 235 and the lower end of the via forming part 235. The outside connection pads 214 connect the wiring board 200 to a mounting board (not illustrated in FIG. 1) such as a mother board. The solder resist layer 216 is provided on the lower surface 212A of the insulating layer 212 so as to cover parts of the outside connection pads 214. The solder resist layer 216 has openings 216A exposing the lower surfaces of the outside connection pads 214.
FIG. 2 through FIG. 8 are views showing a manufacturing method of the related art wiring board. In FIG. 2 through FIG. 8, parts that are the same as the parts shown in FIG. 1 are given the same reference numerals, and explanation thereof is omitted.
The manufacturing method of the related art wiring board 200 is discussed with reference to FIG. 2 through FIG. 8. First, in a step shown in FIG. 2, the piercing holes 221, the piercing electrodes 202, the pads 203, the insulating layer 204 having the openings 223 the wirings 211, and the insulating layer 212 having the openings 233 are formed in the core substrate 201 by a known method. After that, a roughening process such as a desmear process is applied to the insulating layers 204 and 212 so that the upper surface 204A of the insulating layer 204, a surface of each of the pads 203 exposed by the opening 223, the lower surface 212A of the insulating layer 212, and a surface of each of the wirings 211 exposed by the opening 233 is roughened.
Next, in a step shown in FIG. 3, by an electroless plating method, the Cu layer 228 covering the upper surface of a structural body shown in FIG. 2 and a Cu layer 235 covering the lower surface of the structural body shown in FIG. 2 are formed.
Next, in a step shown in FIG. 4, the resist film 241 having openings 241A and 241B for forming wirings are formed on the upper surface of the Cu layer 228 and the resist film 242 having an openings 242A is formed on the lower surface of the Cu layer 235. At this time, the openings 241A for forming the wirings are formed so that an upper surface of the Cu layer 228 corresponding to parts where the wirings 226 are to be formed is exposed. The openings 241B for forming the wirings are formed so that an upper surface of the Cu layer 228 corresponding to parts where the wirings 207 are to be formed is exposed. Furthermore, the openings 242A are formed so that a lower surface of the Cu layer 235 corresponding to parts where the outside connection pads 214 are to be formed is exposed.
Next, in a step shown in FIG. 5, by an electrolytic plating method where the Cu layer 228 is used as a feeding layer, the Cu plating film 229 filling the openings 223 and 233 and the openings 241A and 241B is formed. In addition, by an electrolytic plating method where the Cu layer 235 is used as a feeding layer, the Cu plating film 236 filling the openings 242A is formed. As a result of this, the via forming parts 213 and 225 are formed.
After that, in a step shown in FIG. 6, the resist films 241 and 242 shown in FIG. 5 are removed.
Then in a step shown in FIG. 7, by a wet etching method, an unnecessary part of the Cu layer 228 which is not covered with the Cu plating film 229 and an unnecessary part of the Cu layer 235 which is not covered with the Cu plating film 236 are removed. As a result of this, the wirings 226 and 207 and the outside connection pads 214 are formed. In other words, the wirings 226 and 207 and the outside connection pads 214 are formed by a semi-additive method.
Next, in a step shown in FIG. 8, the solder resist layer 208 having the openings 208A is formed on the upper surface 204A of the insulating layer 204; and the solder resist layer 216 having the openings 216A is formed on the lower surface 212A of the insulating layer 212. As a result of this, the related art wiring board 200 is manufactured. See, for example, Japanese Laid-Open Patent Application Publication No. 10-125818.
FIG. 9 is a view showing problems of the manufacturing method of the related art wiring board.
In FIG. 9, “W1” represents a designated width of the wiring 207 in design; and “W2” represents a designated width of the wiring 226 in design.
However, according to the manufacturing method of the related art wiring board 200, in the step shown in FIG. 7, when the unnecessary parts of the Cu layers 228 and 235 are removed, the parts of the Cu layer 228 and the Cu plating film 229 forming the wirings 207 and 226 are also etched as shown in FIG. 9. Accordingly, the widths of the wirings 207 and 226 become less than the designated widths W1 and W2. Especially when the wirings 207 having a narrow wiring width equal to or less than 10 μm exist, this problem is more serious. The same problem may exist when the outside connection pads 214 are formed by the semi-additive method.